Advanced Hardware & IoT Masterclass Practice Test 2026 | Exa

In a multi-core processor with a shared L3 cache, which cache coherence protocol is most commonly used in modern implementations to maintain data consistency between private L1/L2 caches?

When designing a custom hardware accelerator using an FPGA, which of the following techniques is primarily used to achieve high throughput by processing multiple data elements simultaneously?

A system-on-chip (SoC) uses an AMBA AXI bus for communication between a processor and a high-performance peripheral. Which AXI channel is used by the manager (master) to send the address and control information for a write operation?